Texas Instruments TLV5604 2.7-V to 5.5-V 10-Bit 3-μs Quadruple Digital-to-Analog Converters with Power Down Owner's Manual

TLV5604

2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS

WITH POWER DOWN

SLAS176B – DECEMBER 1997 – REVISED JULY 2002

Four 10-Bit D/A Converters Hardware Power Down (10 n A) Programmable Settling Time Software Power Down (10 n A) of 3 µs or 9 µs Typ

Simultaneous Update

TMS320, (Q)SPI, and Microwire Compatible Serial Interface applications Internal Power-On Reset

Battery Powered Test Instruments

Low Power Consumption:

Digital Offset and Gain Adjustment

5.5 m W, Slow Mode – 5-V Supply

Industrial Process Controls

3.3 m W, Slow Mode – 3-V Supply

Machine and Motion Control Devices

Reference Input Buffers

Communications

Voltage Output Range 2× the Reference

Arbitrary Waveform Generation

Input Voltage Monotonic Over Temperature D OR PW PACKAGE

Dual 2.7-V to 5.5-V Supply (Separate Digital (TOP VIEW)

and Analog Supplies)

DVDD AVDD

description PD REFINAB

LDAC OUTA

The TLV5604 is a quadruple 10-bit voltage output

DIN OUTB

digital-to-analog converter (DAC) with a flexible

SCLK OUTC

4-wire serial interface. The 4-wire serial interface

CS OUTD

allows glueless interface to TMS320, SPI, QSPI,

FS REFINCD

and Microwire serial ports. The TLV5604 is

DGND AGND

programmed with a 16-bit serial word comprised of a DAC address, individual DAC control bits, and a 10-bit DAC value. The device has provision for two supplies: one digital supply for the serial interface (via pins DVDD and DGND), and one for the DACs, reference buffers and output buffers (via pins AVDD and AGND). Each supply is independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins DVDD and DGND), with the DACs operating on a 5-V supply. Of course, the digital and analog supplies can be tied together. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage then DACs C and D. The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The TLV5604C is characterized for operation from 0°C to 70°C. The TLV5604I is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.

Copyright  2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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