Philips 74HC HCT390 Dual Decade Ripple Counter Data Sheet
Summary
Philips 74HC/HCT390 dual decade ripple counter IC data sheet for high-speed CMOS logic, LSTTL pin-compatible. Features two independent 4-bit BCD counters configurable for divide-by-2, 4, 5, 10, 20, 25, 50, or 100 via separate clocks and shared master reset. Covers propagation delays, I/O ratings, power dissipation, pin configuration, and logic diagrams. For digital designers building counters and frequency dividers in industrial and telecom equipment.
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INTEGRATED CIRCUITS
DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT390 Dual decade ripple counter
Product specification December
File under Integrated Circuits, IC06
Page Summary Contents For Philips 74HC HCT390 Dual Decade Ripple Counter Data Sheet
Manual Details
| Brand | Philips |
|---|---|
| Pages | 7 |
| File Size | 42.64 KB |
| Published | July 04, 2026 |
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Frequently Asked Questions
What are the key features of the 74HC/HCT390?
It is a dual 4-bit decade ripple counter offering BCD or bi-quinary configuration, two master reset inputs, and divide-by-2, 4, 5, 10, 20, 25, 50, or 100 capabilities.
How do I achieve BCD decade operation?
Connect the nQ0 output to the nCP1 input of the divide-by-5 section, with the counter input on nCP0.
What is the function of the master reset (nMR) input?
It is an active HIGH asynchronous input that clears the counter; a HIGH level overrides the clocks and sets all four outputs LOW.
What is the typical propagation delay for the 74HC390 (nCP0 to nQ0)?
Typical propagation delay (tPLH/ tPHL) from nCP0 to nQ0 is 14 ns at VCC = 6.0V and Tamb = 25°C.