Philips 74HC HCT161 Presettable Synchronous 4-Bit Binary Counter; Asynchronous Reset Data Manual User Guide
Summary
A synchronous presettable 4-bit binary counter with asynchronous reset from the 74HC/HCT high-speed CMOS logic family, pin-compatible with LSTTL devices. Features synchronous counting and parallel loading, two count enable inputs for n-bit cascading, positive-edge triggered clock, look-ahead carry for simplified serial cascading, and terminal count output for multi-stage connection. Provides asynchronous master reset overriding all other inputs. JEDEC no. 7A compliant. Designed for digital logic designers building frequency dividers, event counters, address generators, and timing circuits in consumer, industrial, and communications equipment.
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INTEGRATED CIRCUITS
DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT161 Presettable synchronous 4-bit binary counter; asynchronous reset
Product specification December
File under Integrated Circuits, IC06
Page Summary Contents For Philips 74HC HCT161 Presettable Synchronous 4-Bit Binary Counter; Asynchronous Reset Data Manual User Guide
Manual Details
| Brand | Philips |
|---|---|
| Pages | 12 |
| File Size | 76.74 KB |
| Published | July 04, 2026 |
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Frequently Asked Questions
What is the maximum clock frequency of the 74HC161?
The maximum clock frequency is 44 MHz.
How does the asynchronous reset work on the 74HC/HCT161?
A LOW on MR sets all Q outputs to LOW regardless of CP, PE, CET and CEP levels.
Is the 74HC/HCT161 compatible with LSTTL?
Yes, it is pin compatible with low power Schottky TTL (LSTTL).