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NATIONAL SEMICONDUCTOR LMX2487E User Guide

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ig rfo rm lta -S ig r D l P tin re th ize

May 2007

LMX2487E 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum™ Frequency Synthesizers with 3.0 GHz Integer PLL

WLAN Standards

General Description The LMX2487E is a low power, high performance delta-sigma

Features

fractional-N PLL with an auxiliary integer-N PLL. It is fabricat- ed using National Semiconductor’s advanced process.

Quadruple Modulus Prescalers for Lower Divide Ratios

With delta-sigma architecture, fractional spurs at lower offset

RF PLL: 16/17/20/21 or 32/33/36/37

frequencies are pushed to higher frequencies outside the loop

IF PLL: 8/9 or 16/17

bandwidth. The ability to push close in spur and phase noise energy to higher frequencies is a direct function of the mod-

Advanced Delta Sigma Fractional Compensation

ulator order. Unlike analog compensation, the digital feed-

12 bit or 22 bit selectable fractional modulus

back technique used in the LMX2487E is highly resistant to

Up to 4th order programmable delta-sigma modulator

changes in temperature and variations in wafer processing. The LMX2487E delta-sigma modulator is programmable up

Features for Improved Lock Times and Programming

to fourth order, which allows the designer to select the opti-

Fastlock / Cycle slip reduction

mum modulator order to fit the phase noise, spur, and lock

time requirements of the system. Integrated time-out counter

Serial data for programming the LMX2487E is transferred via Single word write to change frequencies with Fastlock a three line high speed (20 MHz) MICROWIRE interface. The

Wide Operating Range

LMX2487E offers fine frequency resolution, low spurs, fast

programming speed, and a single word write to change the LMX2487E RF PLL: 3.0 GHz to 7.5 GHz

frequency. This makes it ideal for direct digital modulation

Useful Features

applications, where the N counter is directly modulated with

information. The LMX2487E is available in a 24 lead Digital lock detect output

4.0 X 4.0 X 0.8 mm LLP package.

Hardware and software power-down control On-chip crystal reference frequency doubler.

Applications

RF phase comparison frequency up to 50 MHz

Cellular phones and base stations

2.5 to 3.6 volt operation with ICC = 8.5 m A at 3.0 V

Direct digital modulation applications Satellite and cable TV tuners

Functional Block Diagram

PLLatinum™ is a trademark of National Semiconductor Corporation.

© 2007 National Semiconductor Corporation www.national.com

Page Summary Contents For NATIONAL SEMICONDUCTOR LMX2487E User Guide

Page 1 ig rfo rm lta -S ig r D l P tin re th ize May 2007 LMX2487E 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum™ Frequency Synthesizers with 3.0 GHz Integer PLL WLAN Standards General Descri...
Page 2 Connection Diagram Top View 24-Pin LLP (SQ) Pin Descriptions Pin # Pin Name I/O Pin Description GND Ground Substrate. This is on the bottom of the package and must be grounded. CPout RF RF PLL charge ...
Page 3 Absolute Maximum Ratings (Notes 1, 2) Value Parameter Symbol Units Min Typ Max Power Supply Voltage VCC -0.3 4.25 Voltage on any pin with GND = 0V Vi -0.3 VCC+0.3 Storage Temperature Range Ts -65 +150...
Page 4 Value Symbol Parameter Conditions Units Min Typ Max RF_CPG = 0 VCPout RF = VCC/2 RF Charge Pump Sink RF_CPG = 1 ICPout RFSINK Current VCPout RF = VCC/2 (Note 4) µA RF_CPG = 15 VCPout RF = VCC/2 RF Cha...
Page 5 Value Symbol Parameter Conditions Units Min Typ Max PHASE NOISE RF_CPG = 0 -202 RF Synthesizer RF_CPG = 1 -204 LF1Hz RF Normalized Phase Noise RF_CPG = 3 -206 d Bc/Hz Contribution(Note 6) RF_CPG = 7 -...
Page 6 Typical Performance Characteristics : Sensitivity (Note 7) RF PLL Fin Sensitivity TA = 25°C, RF_P = 32 RF PLL Fin Sensitivity VCC = 3.0 V, RF_P = 32 www.national.com
Page 7 IF PLL Fin Sensitivity TA = 25°C, IF_P = 16 IF PLL Fin Sensitivity VCC = 3.0 V, IF_P = 16 www.national.com
Page 8 OSCin Sensitivity TA = 25°C, OSC_2X = 0 OSCin Sensitivity VCC = 3.0 V, OSC_2X = 0 www.national.com
Page 9 OSCin Sensitivity TA = 25°C, OSC_2X =1 OSCin Sensitivity VCC = 3.0 V, OSC_2X = 1 www.national.com
Page 10 Typical Performance Characteristic : Fin RF Input Impedance (Note 7) Fin RF Input Impedance Frequency (MHz) Real (Ohms) Imaginary (Ohms) www.national.com
Page 11 Typical Performance Characteristic : Fin IF Input Impedance (Note 7) Fin IF Input Impedance Frequency (MHz) Real (Ohms) Imaginary (Ohms) www.national.com
Page 12 Typical Performance Characteristic : OSCin Input Impedance (Note 7) Frequency Powered Up Powered Down (MHz) Real Imaginary Magnitude Real Imaginary Magnitude www.national.com
Page 13 Typical Performance Characteristics : Currents (Note 7) Power Supply Current CE = High RF PLL Charge Pump Current VCC = 3.0 Volts www.national.com
Page 14 IF PLL Charge Pump Current VCC = 3.0 Volts Charge Pump Leakage RF PLL VCC = 3.0 Volts www.national.com
Page 15 Charge Pump Leakage IF PLL VCC = 3.0 Volts Note 7: Typical performance characteristics do not imply any sort of guarantee. Guaranteed specifications are in the electrical characteristics section. www....
Page 16 Bench Test Setups Charge Pump Current Measurement Procedure The above block diagram shows the test procedure for testing the RF and IF charge pumps. These tests include absolute current level, mismatc...
Page 17 Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV I2 = Charge Pump Sink Current at VCPout = Vcc/2 I3 = Charge Pump Sink Current at VCPout = ΔV I4 = Charg...
Page 18 Frequency Input Pin DC Blocking Capacitor Corresponding Default Counter Value MUX Value Counter OSCin 1000 p F RF_R / 2 Fin RF 100 p F// 1000 p F RF_N / 2 502 + 2097150 / Fin IF 100 p F IF_N / 2 OSCin...
Page 19 Input Impedance Measurement Procedure The above block diagram shows the test setup used for measuring the input impedance for the LMX2487E. The DC blocking capacitor used between the input SMA connect...
Page 20 erences available, such as the one given at the end of the Functional Description (Note 8) functional description block. 1.0 GENERAL 1.5 N COUNTERS AND HIGH FREQUENCY INPUT PINS The LMX2487E consists ...
Page 21 CE Pin RF_PD ATPU PLL State Bit Enabled + Write to RF N Counter Low Powered Down (Asynchronous) High Yes Powered Up High No Powered Up High No Powered Down ( Asynchronous ) 1.7 DIGITAL LOCK DETECT OPE...
Page 22 1.8 CYCLE SLIP REDUCTION AND FASTLOCK 1.8.1 Using Cycle Slip Reduction (CSR) to Avoid Cycle Slipping The LMX2487E offers both cycle slip reduction (CSR) and Fastlock with timeout counter support. This...
Page 23 never recommended. In this case, the value for R2p is typi- ally one-half or one-fourth. There are trade-offs between frac- cally about 80% of what it would be for a second order filter. tional spurs,...
Page 24 Programming Description 2.0 GENERAL PROGRAMMING INFORMATION The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program the R counter, the N counter, a...
Page 25 Quick Start Register Map Although it is highly recommended that the user eventually take advantage of all the modes of the LMX2487E, the quick start register map is shown in order for the user to get ...
Page 26 2.1 R0 REGISTER Note that this register has only one control bit, so the N counter value to be changed with a single write statement to the PLL. REGISTER DATA[22:0] C0 R0 RF_N[10:0] RF_FN[11:0] 2.1.1 ...
Page 27 2.2 R1 REGISTER REGISTER DATA[19:0] C3 C2 C1 C0 R1 RF_PD RF_P RF_R[5:0] RF_FD[11:0] 2.2.1 RF_FD[11:0] -- RF PLL Fractional Denominator The function of these bits are described in section 2.6.2. 2.2.2 ...
Page 28 2.3 R2 REGISTER REGISTER DATA[19:0] C3 C2 C1 C0 R2 IF_PD IF_N[18:0] 2.3.1 IF_N[18:0] -- IF N Divider Value IF_N Counter Programming with the 8/9 Prescaler (IF_P=0) IF_N[18:0] N Value IF_B IF_A ≤23 N v...
Page 29 2.4 R3 REGISTER REGISTER DATA[19:0] C3 C2 C1 C0 R3 ACCESS[3:0] RF_CPG[3:0] IF_R[11:0] 2.4.1 IF_R[11:0] -- IF R Divider Value For the IF R divider, the R value is determined by the IF_R[11:0] bits in t...
Page 30 Register
Page 31 2.5 R4 REGISTER This register controls the conditions for the RF PLL in Fastlock. REGISTER DATA[19:0] C3 C2 C1 C0 DITH FM OSC_ OSC_ IF_ RF_ MUX R4 ATPU IF_P [1:0] [1:0] 2X OUT CPP CPP [3:0] 2.5.1 MUX[...
Page 32 2.5.5 OSC_OUT Oscillator Output Buffer Enable OSC_OUT OSCout Pin Disabled (High Impedance) Buffered output of OSCin pin 2.5.6 OSC2X -- Oscillator Doubler Enable When this bit is set to 0, the oscillat...
Page 33 2.6 R5 REGISTER REGISTER DATA[19:0] C3 C2 C1 C0 R5 RF_FD[21:12] RF_FN[21:12] 2.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[1] } In the case that the ACCESS[1] bit is 0, ...
Page 34 2.7 R6 REGISTER REGISTER DATA[19:0] C3 C2 C1 C0 R6 CSR[1:0] RF_CPF[3:0] RF_TOC[13:0] 2.7.1 RF_TOC -- RF Time Out Counter and Control for FLout RF Pin The RF_TOC[13:0] word controls the operation of th...
Page 35 CSR CSR State Sample Rate Reduction Factor Disabled Enabled 1/2 Enabled 1/4 Enabled 1/16 www.national.com
Page 36 2.8 R7 REGISTER REGISTER Data[19:0] C3 C2 C1 C0 2.8.1 DIV4 -- RF Digital Lock Detect Divide By 4 Because the digital lock detect function is based on a phase error, it becomes more difficult to detect...
Page 37 Physical Dimensions inches (millimeters) unless otherwise noted Plastic Quad LLP (SQ), Bottom View Order Number LMX2487ESQXfor 4500 Unit Reel Order Number LMX2487ESQ for 1000 Unit Reel NS Package Numb...
Page 38 ig rf rm lt -S ig ti re th iz Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANT...