National Semiconductor DS92LV16 datasheet user manual

Summary

The DS92LV16 is a high-speed 16-Bit Bus LVDS Serializer/Deserializer (SERDES) designed to efficiently convert parallel data into robust serial streams up to 80 MHz. This device simplifies complex signal routing by eliminating skew issues, enabling reliable full-duplex data transfer over PCBs and backplanes. The manual provides comprehensive detailed specifications, including electrical characteristics, loopback modes for testing line integrity, operating temperature details, and system integration guidelines. It is essential hardware for systems engineers developing compact, high-speed communication equipment that requires low power consumption and maximum signal fidelity.

DS92LV16
- General Description
- Features
- Block Diagram
- Absolute Maximum Ratings
- Recommended Operating Conditions
- Electrical Characteristics
- Serializer Timing Requirements for TCLK
- Serializer Switching Characteristics
- Deserializer Timing Requirements for REFCLK
- Deserializer Switching Characteristics
- AC Timing Diagrams and Test Circuits
  - FIGURE 1. "Worst Case" Serializer ICC Test Pattern
  - FIGURE 2. "Worst Case" Deserializer ICC Test Pattern
  - FIGURE 3. Serializer Bus LVDS Output Load and Transition Times
  - FIGURE 4. Deserializer CMOS/TTL Output Load and Transition Times
  - FIGURE 5. Serializer Input Clock Transition Time
  - FIGURE 6. Serializer Setup/Hold Times
  - FIGURE 7. Serializer TRI-STATE Test Circuit and Timing
  - FIGURE 8. Serializer PLL Lock Time, SYNC Timing and PWRDN TRI-STATE Delays
  - FIGURE 9. Serializer Delay
  - FIGURE 10. Deserializer Delay
  - FIGURE 11. Deserializer Setup and Hold Times
  - FIGURE 12. Deserializer TRI-STATE Test Circuit and Timing
  - FIGURE 13. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
  - FIGURE 14. Deserializer PLL Lock Time from SyncPAT
  - FIGURE 15. Deterministic Jitter and Ideal Bit Position
  - FIGURE 16. Deserializer Noise Margin (tRNMI) and Sampling window
  - FIGURE 17. VOD Diagram
  - FIGURE 18. Icc vs Freq
  - FIGURE 19. Icc vs Freq (Rx only)
  - FIGURE 20. Icc vs Freq (Tx only)
- Functional Description
- Initialization
- Data Transfer
- Resynchronization
- Powerdown
- TRI-STATE
- Loopback Test Operation
- Application Information
- Pin Diagram
- Pin Descriptions
- Physical Dimensions

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Manual Details

Brand	National
Pages	19
File Size	397.09 KB
Published	June 18, 2026

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Frequently Asked Questions

What does the DS92LV16 handle regarding data conversion?

It translates a 16-bit parallel bus into a BLVDS serial stream with embedded clock information.

How can I test the data transmission line integrity without external equipment?

The device supports local loopback and line loopback modes to check transceiver integrity.

Over what temperature range does this SERDES operate nominally?

It operates in an industrial temperature range from -40°C to +85°C.

Is additional power supply required for the differential data path control/EMI reduction?

No external PLL components are required, and it utilizes coupled equal and opposite currents to control EMI.

National Semiconductor DS92LV16 datasheet user manual

Summary

FIGURE 1. "Worst Case" Serializer ICC Test Pattern

FIGURE 2. "Worst Case" Deserializer ICC Test Pattern

FIGURE 3. Serializer Bus LVDS Output Load and Transition Times

FIGURE 4. Deserializer CMOS/TTL Output Load and Transition Times

FIGURE 5. Serializer Input Clock Transition Time

FIGURE 6. Serializer Setup/Hold Times

FIGURE 7. Serializer TRI-STATE Test Circuit and Timing

FIGURE 8. Serializer PLL Lock Time, SYNC Timing and PWRDN TRI-STATE Delays

FIGURE 9. Serializer Delay

FIGURE 10. Deserializer Delay

FIGURE 11. Deserializer Setup and Hold Times

FIGURE 12. Deserializer TRI-STATE Test Circuit and Timing

FIGURE 13. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays

FIGURE 14. Deserializer PLL Lock Time from SyncPAT

FIGURE 15. Deterministic Jitter and Ideal Bit Position

FIGURE 16. Deserializer Noise Margin (tRNMI) and Sampling window

FIGURE 17. VOD Diagram

FIGURE 18. Icc vs Freq

FIGURE 19. Icc vs Freq (Rx only)

FIGURE 20. Icc vs Freq (Tx only)

DS92LV16

General Description

Features

Block Diagram

Absolute Maximum Ratings

Recommended Operating Conditions

Electrical Characteristics

Serializer Timing Requirements for TCLK

Serializer Switching Characteristics

Deserializer Timing Requirements for REFCLK

Deserializer Switching Characteristics

AC Timing Diagrams and Test Circuits

FIGURE 1. "Worst Case" Serializer ICC Test Pattern

FIGURE 2. "Worst Case" Deserializer ICC Test Pattern

FIGURE 3. Serializer Bus LVDS Output Load and Transition Times

FIGURE 4. Deserializer CMOS/TTL Output Load and Transition Times

FIGURE 5. Serializer Input Clock Transition Time

FIGURE 6. Serializer Setup/Hold Times

FIGURE 7. Serializer TRI-STATE Test Circuit and Timing

FIGURE 8. Serializer PLL Lock Time, SYNC Timing and PWRDN TRI-STATE Delays

FIGURE 9. Serializer Delay

FIGURE 10. Deserializer Delay

FIGURE 11. Deserializer Setup and Hold Times

FIGURE 12. Deserializer TRI-STATE Test Circuit and Timing

FIGURE 13. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays

FIGURE 14. Deserializer PLL Lock Time from SyncPAT

FIGURE 15. Deterministic Jitter and Ideal Bit Position

FIGURE 16. Deserializer Noise Margin (tRNMI) and Sampling window

FIGURE 17. VOD Diagram

FIGURE 18. Icc vs Freq

FIGURE 19. Icc vs Freq (Rx only)

FIGURE 20. Icc vs Freq (Tx only)

Functional Description

Initialization

Data Transfer

Resynchronization

Powerdown

TRI-STATE

Loopback Test Operation

Application Information

Pin Diagram

Pin Descriptions

Physical Dimensions

Page 1 Text Content

Manual Details

Frequently Asked Questions

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