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ATMEL AVR Microcontroller ATmega32M1 Data Sheet

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BDTIC www.bdtic.com/ATMEL

Features High Performance, Low Power AVR ® 8-bit Microcontroller Advanced RISC Architecture 131 Powerful Instructions - Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 1 MIPS throughput per MHz On-chip 2-cycle Multiplier Data and Non-Volatile Program Memory

16K/32K/64K Bytes Flash of In-System Programmable Program Memory 8-bit

Endurance: 10,000 Write/Erase Cycles

Microcontroller

Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program

True Read-While-Write Operation 512/1024/2048 Bytes of In-System Programmable EEPROM

Endurance: 50,000 Write/Erase Cycles Programming Lock for Flash Program and EEPROM Data Security Bytes In-System 1024/2048/4096 Bytes Internal SRAM On Chip Debug Interface (debug WIRE) Programmable CAN 2.0A/B with 6 Message Objects - ISO 16845 Certified (1)

LIN 2.1 and 1.3 Controller or 8-Bit UART Flash

One 12-bit High Speed PSC (Power Stage Controller) (only ATmega16/32/64M1) Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time Variable PWM duty Cycle and Frequency

ATmega16M1

Synchronous Update of all PWM Registers Auto Stop Function for Emergency Event ATmega32M1 Peripheral Features One 8-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode ATmega64M1 and Capture Mode

One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare ATmega32C1

Mode and Capture Mode

ATmega64C1

One Master/Slave SPI Serial Interface 10-bit ADC Up To 11 Single Ended Channels and 3 Fully Differential ADC Channel Pairs Programmable Gain (5x, 10x, 20x, 40x) on Differential Channels

Automotive

Internal Reference Voltage Direct Power Supply Voltage Measurement 10-bit DAC for Variable Voltage Reference (Comparators, ADC) Four Analog Comparators with Variable Threshold Detection Preliminary 100µA ±3% Current Source (LIN Node Identification) Interrupt and Wake-up on Pin Change Programmable Watchdog Timer with Separate On-Chip Oscillator

Summary

On-chip Temperature Sensor Special Microcontroller Features Low Power Idle, Noise Reduction, and Power Down Modes Power On Reset and Programmable Brown Out Detection In-System Programmable via SPI Port High Precision Crystal Oscillator for CAN Operations (16 MHz)

1. See certification on Atmel web site. And note on Section 16.4.3 on page 175. 7647DS–AVR–08/08

Page Summary Contents For ATMEL AVR Microcontroller ATmega32M1 Data Sheet

Page 1 BDTIC www.bdtic.com/ATMEL Features High Performance, Low Power AVR ® 8-bit Microcontroller Advanced RISC Architecture 131 Powerful Instructions - Most Single Clock Cycle Execution 32 x 8 General Purpo...
Page 2 ATmega16/32/64/M1/C1 Internal Calibrated RC Oscillator ( 8 MHz) On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz) Operating Voltage: 2.7V - 5.5V Extended Operating Temperature: -40°C to +125...
Page 3 1. Pin Configurations Figure 1-1. ATmega16/32/64M1 TQFP32/QFN32 (7*7 mm) Package. ATmega32/64M1 TQFP32/QFN32 (PCINT18/PSCIN2/OC1A/MISO_A) PD2 PB4 (AMP0+/PCINT4) (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 ...
Page 4 ATmega16/32/64/M1/C1 Figure 1-2. ATmega32/64C1 TQFP32/QFN32 (7*7 mm) Package ATmega32/64C1 TQFP32/QFN32 (PCINT18/OC1A/MISO_A) PD2 PB4 (AMP0+/PCINT4) (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 PB3 (AMP0-/P...
Page 5 1.1 Pin Descriptions Table 1-1. Pin out description QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function GND Power Ground: 0V reference AGND Power Analog Ground: 0V reference for ana...
Page 6 ATmega16/32/64/M1/C1 Table 1-1. Pin out description (Continued) QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function PSCIN1 (PSC Digital Input 1) OC1B (Timer 1 Output Compare B) PC1 ...
Page 7 Table 1-1. Pin out description (Continued) QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function ADC1 (Analog Input Channel 1) RXD (UART Rx data) RXLIN (LIN Receive Input) PD4 I/O ICP...
Page 8 ATmega16/32/64/M1/C1 2.1 Block Diagram Figure 2-1. Block Diagram Data Bus 8-bit Program Status Interrupt Flash Program Unit Counter and Control Memory SPI Unit 32 x 8 Instruction General Watchdog Regi...
Page 9 The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART and interrupt system to continue functioning. The Power-down mode saves the regis- ter contents but freeze...
Page 10 ATmega16/32/64/M1/C1 2.3.3 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive charac...
Page 11 The various special features of Port E are elaborated in “Alternate Functions of Port E” on page 78 and “Clock Systems and their Distribution” on page 29. 2.3.7 AVCC AVCC is the supply voltage pin for...
Page 12 ATmega16/32/64/M1/C1 3. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x FF) Reserved (0x FE) Reserved (0x FD) Reserved (0x FC) Reserved (0x FB) Reserved (0x FA) ...
Page 13 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x BE) Reserved (0x BD) Reserved (0x BC)(5) PIFR PEV2 PEV1 PEV0 PEOP (0x BB)(5) PIM PEVE2 PEVE1 PEVE0 PEOPE (0x BA)(5) PMIC2 POVEN2 P...
Page 14 ATmega16/32/64/M1/C1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7C) ADMUX REFS1 REFS0 ADLAR MUX3 MUX2 MUX1 MUX0 (0x7B) ADCSRB ADHSM ISRCEN AREFEN ADTS3 ADTS2 ADTS1 ADTS0 (0x7...
Page 15 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1A (0x3A) GPIOR2 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 0x19 (0x39) GPIOR1 GPIOR17 GPIOR16 GPIOR15 GPIOR14 ...
Page 16 ATmega16/32/64/M1/C1 4. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr ...
Page 17 Mnemonics Operands Description Operation Flags #Clocks BRIE Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 Non...
Page 18 ATmega16/32/64/M1/C1 Mnemonics Operands Description Operation Flags #Clocks POP Rd Pop Register from Stack Rd ← STACK None MCU CONTROL INSTRUCTIONS NOP No Operation None SLEEP Sleep (see specific desc...
Page 19 5. Errata 5.1 Errata Summary 5.1.1 ATmega32M1/C1 Rev. C (Mask Revision) The AMPCMPx bits return 0 5.1.2 ATmega32M1/C1 Rev. B (Mask Revision) The AMPCMPx bits return 0 No comparison when amplifier is u...
Page 20 ATmega16/32/64/M1/C1 a. Slave task of master node: Before enabling the HEADER, the master must set the appropriate LIN13 bit value in LINCR register. b. For slaves nodes, the workaround is in 2 parts:...
Page 21 6. Ordering Information Figure 6-1. ATmega32M1 engineering samples delivery only. Automotive qualification not yet fully completed. Memory Size PSC Power Supply Ordering Code Package Operation Range 3...
Page 22 ATmega16/32/64/M1/C1 7. Package Information Package Type MA, 32 - Lead, 7x7 mm Body Size, 1.0 mm Body Thickness MA 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) PV, 32-Lead, 5.0x5.0...
Page 23 7.1 TQFP32 ATmega16/32/64/M1/C1 7647DS–AVR–08/08
Page 24 ATmega16/32/64/M1/C1 7.2 QFN32 7647DS–AVR–08/08