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BDTIC www.BDTIC.com/ATMEL Features 80C51 Compatible CPU Core High-speed Architecture X2 Speed Improvement Capability (6 Clocks/Machine Cycle) 16 MHz in Standard or X2 mode 256 Bytes RAM 256 Bytes XRAM...
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Block Diagram XTAL1 Osc EXRAM RAM ROM XTAL2 PCA SPI C51 CORE IB-bus Timer 0 INT Parallel I/O Ports IN Timer 1 Ctrl Port 1 Port 3 Port 4 IN Notes: 1. Alternate function of Port 1. 2. Alternate function...
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Pin Configurations P3.2/DIG0/INT0 P1.7/CEX4/SS P3.4/DIG1/T0 P1.6/CEX3 P1.5/CEX2 P3.6/SPICK VSS P1.4/CEX1 SSOP16 VCC P1.3/CEX0 RST/VPP P1.2/ECI/DIG2 XTAL2 P1.1/MOSI XTAL1 P1.0/MISO P3.2/DIG0/INT0 P3.3/...
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Pin Description Mnemonic Type Name and Function VSS Ground: 0V reference VCC Power Supply: 3.0V or 5.5V P1.0 - P1.7 I/O Port 1: Port 1 is an 8-bit programmable I/O port with internal pull-up Alternate...
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Clock The Errata Sheet core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages: Divides frequency crystals by 2 (cheaper crystals) while keeping...
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Figure 1. Clock CPU Generation Diagram PCON.0 IDL X2 CKCON.0 FCLK_PERIPH XTAL1 XTAL2 PD PCON.1 FT0 Clock FT1 Clock FPCA Clock FSPI Clock X2 CKCON0.0 Peripheral Clock Symbol PCAX2 T1X2 T0X2 CKCON0.7 CK...
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Figure 2. Mode Switching Waveforms XTAL1 XTAL2 X2 Bit CPU Clock X2 Mode STD Mode STD Mode The X2 bit in the CKCON register (See Table 1) allows switching from 12 clock cycles per instruction to 6 cloc...
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Registers Table 1. CKCON0 Register CKCON0 (S:8Fh) Clock Control Register PCAX2 T1X2 T0X2 X2 Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this ...
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Table 2. CKCON1 Register CKCON1 (S:AFh) Clock Control Register SPIX2 Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value...
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SFR Mapping The Special Function Registers (SFRs) of the AT8x C5103 belong to the following categories: C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P1, P3, P4, P1M1, P1M2,...
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Table 3. SFR Addresses and Reset Values CH CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H F8h FFh CL CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L E8h EFh ACC P1M2 P3M2 CCON CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 DF 00X0 0...
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Ports The AT8x C5103 has 3 I/O ports, port 1, port 3 and port 4. Except RST, and port 4, all port 1 and port 3 I/O port pins on the AT8x C5103 may be software configured to one of four types on a bit-...
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Figure 3. Quasi-Bi-directional Output 2 CPU PClock Delay Strong Weak Port latch Data Input Data Open Drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-do...
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Input Only Configuration The input only configuration is a pure input with neither pull-up nor pull-down. The input only configuration is shown in Figure 6. Figure 6. Input Only Input Data Ports Descr...
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Table 6. P3M1 Register P3M1 Address (D5h) Bit Number Mnemonic Description Port Output configuration bit See Table 2 for configuration definition Reset Value = 0000 0000 Table 7. P3M2 Register P3M2 Add...
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Dual-data Pointer The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. Register (DPTR) The dual DPTR structure is a way by which the device will...
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Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search...) are well served by using o...
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Serial Port Interface The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. (SPI) Featu...
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Slave Select (SS) Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can drive th...
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Functional Description Figure 9 shows a detailed structure of the SPI module. Figure 9. SPI Module Block Diagram Internal Bus SPDAT Shift Register Int Clk Clock /8 Receive Data Register /16 Pin Divide...
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Figure 10. Full-Duplex Master-Slave Interconnection 8-bit Shift Register 8-bit Shift Register MISOMISO SPI SCK SCK Clock Generator Master MCU Slave MCU Master Mode The SPI operates in Master Mode when...
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Figure 11. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB MISO (from Slave) bit6 bit5 bit4 ...
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Error Conditions The following flags in the SPSTA signal SPI error conditions. Mode Fault (MODF) Mode Fault error in Master Mode SPI indicates that the level on the Slave Select (SS) pin is inconsiste...
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Figure 14. SPI Interrupt Requests Generation SPI Transmitter SPI CPU Interrupt Request CPU Interrupt Request SPI Receiver/Error CPU Interrupt Request SSDIS Registers There are three registers in the m...
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Bit Number Bit Mnemonic R/W Mode Description 100: FCLK PERIPH /32 101: FCLK PERIPH /64 SPR0 R/W 110: FCLK PERIPH /128 111: Don’t Use Reset Value = 00010100b Serial Peripheral Status Register The Seria...
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Serial Peripheral Data Register The Serial Peripheral Data Register (Table 13) is a read/write buffer for the receive data (SPDAT) register. A write to SPDAT places data directly into the shift regist...
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Timers/Counters The Errata Sheet implements two general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of mode...
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Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see...
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Mode 3 (Two 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 18). This mode is provided for applications requiring an additional 8- ...
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Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (...
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Registers Table 14. TCON Register TCON (S:88h) Timer/Counter Control Register TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Bit Number Mnemonic Description Timer 1 Overflow Flag TF1 Cleared by hardware when pro...
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Table 15. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic Description Timer 1 Gating Control Bit GATE1 Clear to enable Ti...
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Table 17. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 0 Reset Value = 0000 0000b Table 18. TH1 Register TH1 (S:8Dh) Timer 1 High Byte R...
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Power Management Table 20. PCON Register PCON - Power Control Register (87h) GF1 GF0 PD IDL Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this ...
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Power-down Mode To save maximum power, a power-down mode can be invoked by software (refer to Table 20, PCON register). In power-down mode, the oscillator is stopped and the instruction that invoked p...
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Programmable The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- Counter Array (P...
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PCA Timer Figure 21. PCA Timer/Counter To PCA Modules Fosc/12 Fosc/4 Overflow It CH CL T0 OVF 16-bit Up/Down Counter CIDL CPS1 CPS0 ECF 0x D9WDTE CF CR CCF3 CCF2 CCF1 CCF0 0x D8CCF4 Table 22. CMOD: PC...
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The CMOD SFR includes three additional bits associated with the PCA (See Figure and Table 21). The CIDL bit which allows the PCA to stop during idle mode. The WDTE bit which enables or disables the wa...
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Figure 22. PCA Interrupt System CF CR CCF4 CCF3 CCF2 CCF1 CCF0 PCA Timer/Counter Module 0 Module 1 To Interrupt Priority Decoder Module 2 Module 3 Module 4 IE.6 IE.7 ECF ECCFn CCAPMn.0CMOD.0 EC EA PCA...
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Table 24 shows the CCAPMn settings for the various PCA functions. Table 24. CCAPMn: PCA Modules Compare/Capture Control Registers CCAPM0 (0DAH) CCAPMn CCAPM1 (0DBH) Address CCAPM2 (0DCH) n = 0 - 4 CCA...
