ANALOG DEVICES ADG5204 Product Data Handbook Rev 0

High Voltage, Latch-Up Proof, 4-Channel Multiplexer

ADG5204 FEATURES FUNCTIONAL BLOCK DIAGRAM Latch-up proof ADG5204 3 p F off source capacitance

26 p F off drain capacitance

−0.6 p C charge injection

Low leakage: 0.4 n A maximum at 85°C

±9 V to ±22 V dual-supply operation

1 OF 4 9 V to 40 V single-supply operation DECODERS

48 V supply maximum ratings

A0 A1 EN

Fully specified at ±15 V, ±20 V, +12 V, and +36 V

Figure 1.

VSS to VDD analog signal range

APPLICATIONS Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG5204 is a complementary metal oxide semiconductor 1. Trench Isolation Guards Against Latch-Up. (CMOS) analog multiplexer, comprising four single channels. A dielectric trench separates the P and N channel transistors,

thereby preventing latch-up even under severe overvoltage

The ultralow capacitance and charge injection of these switches

conditions.

make them ideal solutions for data acquisition and sample-and-

2. Ultralow Capacitance and <1 p C Charge Injection.

hold applications, where low glitch and fast settling are required.

3. Dual-Supply Operation.

Fast switching speed together with high signal bandwidth make

For applications where the analog signal is bipolar, the

the ADG5204 suitable for video signal switching.

ADG5204 can be operated from dual supplies up to ±22 V. 8-

The ADG5204 is designed on a trench process, which guards

4. Single-Supply Operation.

against latch-up. A dielectric trench separates the P and N

For applications where the analog signal is unipolar, the

channel transistors, thereby preventing latch-up even under

ADG5204 can be operated from a single rail power supply

severe overvoltage conditions.

up to 40 V.

The ADG5204 switches one of four inputs to a common output, 5. 3 V Logic-Compatible Digital Inputs. D, as determined by the 3-bit binary address lines, A0, A1, and VINH = 2.0 V, VINL = 0.8 V. EN. Logic 0 on the EN pin disables the device. Each switch con- 6. No VL Logic Power Supply Required. ducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action.

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