Saving Power with Atmel PLDs - ATMEL Technical Documentation

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Saving Power with Atmel PLDs

Introduction As shown in equation 1, a designer may be able to reduce the overall power con-

Many designers today are looking for

sumpt ion is her des ign by

ways to reduce power consumption in

reducing the supply voltage, pin capaci-

their designs to meet expanding market

tive loading, or operating frequency. Erasable

demands for portable and battery-oper-

However, these alternatives are usually

ated products. With the push to add

not practical. Another alternative a Programmable

more features to these products while

designer can choose, as equation 2

maintaining the same board size and

shows, is to use parts that consume as Logic Device

power budget, Programmable Logic

little standby power as possible during

Devices with the low power consumption

idle periods when the device is not

are playing a larger role in the design of

responding to input stimulus. Atmel’s

these products. These devices allow the Application

Low-power PLDs are ideally suited for

designer to add more features in the

this purpose.

same board space, yet be able to main- Note tain or decrease the overal l power

consumption of the system. Atmel offers Power Consumption

a variety of PLDs, in several density

Savings with Atmel ITD

classes with pin counts ranging form 20

to 160 pins, that lower power consump- tion significantly by Atmel’s proprietary

Atmel Low- or Zero-power PLDs include

Input Transition Detection (ITD) technol-

an input transition detection (ITD) fea-

ogy. ITD capable PLDs are indicated by

ture, indicated by the “L” or “Z” in the part

a “L” or “Z” in the suffix of the part name.

number suffix. These PLDs save power by automatically powering down to a “standby” or “sleep” mode when no sig-

Power Consumption for

nal transitions occur on the inputs or

internal feedback nodes of the device. When an input signal transition next

Before discussing the detailed features

occurs, the ITD feature “wakes up” the

of Atmel’s Low-power PLDs, it is impor-

device returning it to the active mode.

tant to point out the two components for

Figure 1 shows the Average ICC vs. Fre-

PLD power consumption.

quency characterist ics for Atmel’s

1. Paverage = n CLoad Fop (Vsupply)

standard and low-power PLDs. For fre-

2. Pstandby = ICC,SB Vsupply =

quencies less than Factive, a low-power

Standby Power when the device

device will automatically go through

is powered down

active and standby cycles to reduce the

Where: average current consumption. Com-

pared with a standard power device,

Paverage = average power con-

which always remains active, low-power

sumed while outputs are switching

PLDs offer significant power savings. As

Cload = load capacitance on each

the input signal frequency increases, the

output pin

percentage of time a low-power device is

n = number of output pins

active will also increase proportionally

switching

until Factive is approached. For frequen-

Fop = Frequency of operation cies greater than or equal to Factive, a

low-power device will consume about

Vsupply = supply voltage. Rev. 0457E–09/00

the same amount of current as a stan- dard-power device.