PHILIPS PDI1394P21 3-port Physical Layer Interface Data Sheet User Manual
Summary
This sophisticated physical layer interface is designed for building high-performance, three-port nodes in IEEE 1394/FireWire networks. It provides robust digital and analog transceiver functions, supporting speeds up to 400 Mbits/s. The comprehensive manual details its full compliance with IEEE standards, advanced features like power monitoring, multi-speed concatenation, and automatic link management. Ideal for electronics engineers designing complex data communication systems requiring reliable and highly interoperable connectivity in professional networking applications.
Page 1 Text Content
INTEGRATED CIRCUITS查询PDI1394P21供应商
PDI1394P21 3-port physical layer interface
Objective specification 1999 Jul 09
Page Summary Contents For PHILIPS PDI1394P21 3-port Physical Layer Interface Data Sheet User Manual
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INTEGRATED CIRCUITS查询PDI1394P21供应商 PDI1394P21 3-port physical layer interface Objective specification 1999 Jul 09
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 1.0 FEATURES Fully supports provisions of IEEE 1394–1995 Standard for high Interface to link-layer controller s...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 4.0 PIN CONFIGURATION LREQ AGND SYSCLK /L TPBIAS2 DGND TPA2+ /R CTL0 TPA2– CTL1 TPB2+ DVDD /IS TPB2– LL D0 AVDD...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface Name Description I/OPin Numbers Pin Type C/LKON CMOS 5V tol I/O Bus Manager Contender programming input and lin...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface Name Description I/OPin Numbers Pin Type /RESET CMOS 5V tol Logic reset input. Asserting this terminal low rese...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 6.0 BLOCK DIAGRAM CPS LPS RECEIVED DATA CABLE POWER CPS DECODER/ /ISO DETECTOR RETIMER C/LKON SYSCLK LREQ CABLE...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface data bits are split into two-, four- or eight-bit parallel streams hard-wired high or low as a function of the ...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 8.0 ABSOLUTE MAXIMUM RATINGS 1 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are re...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 10.0 CABLE DRIVER LIMITS SYMBOL PARAMETER TEST CONDITION UNIT MIN TYP MAX VOD Differential output voltage 56 Ω ...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 12.0 OTHER DEVICE I/O SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT Peak 1 tbf m A Transmit 2 tbf m A DD Sup...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 13.0 THERMAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION UNIT MIN TYP MAX RΘj A Junction-to-free-air...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 16.0 INTERNAL REGISTER CONFIGURATION There are 16 accessible internal registers in the PDI1394P21. The The conf...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface FIELD DESCRIPTIONTYPESIZE Pwr_Class Rd/Wr Node power class. This field indicates this node’s power consumption ...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface The Port Status page provides access to configuration and status information for each of the ports. The port is...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface The Vendor Identification page is used to identify the vendor/manufacturer and compliance level. The page is se...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 17.0 APPLICATION INFORMATION CPS CABLE POWER PDI1394P21 PAIR TPBIAS TPAn+ CABLE PAIR A TPAn– CABLE PORT TPBn+ C...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 17.1 External Component Connections LK 12 p F12 p F 24.576 MHz LA IN /IS /IS LL LE LL LREQ AGND LL SYSCLK TPBIA...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 17.2 Using the PDI1394P21 with a non-P1394a 17.3 /Reset and Power Down link layer Forcing the /RESET pin low ca...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 18.0 PRINCIPLES OF OPERATION The PDI1394P21 is designed to operate with an LLC such as the terminals are used f...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface LR0 LR1 LR2 LR3 LR(n–2) LR(n–1) SV01758 Figure 10. LREQ Request Stream 18.1 LLC service request For a bus reque...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface For a write register request, the length of the LREQ bit stream is end of the received packet and the start of ...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 18.2 Status transfer A status transfer is initiated by the PHY when there is status subsequently interrupts the...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 18.3 Receive Whenever the PHY detects the data-prefix state on the serial bus, it PDI1394P21 sends at least one...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface The sequence of events for a null packet reception is as follows: Data-on indication. The PHY asserts the data-...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface 18.4 Transmit When the LLC issues a bus request through the LREQ terminal, the CTL terminals change direction b...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface The sequence of events for a cancelled/null packet transmission is Null transmit termination. The null transmit...
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 1999 Jul 09
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Philips Semiconductors Objective specification PDI1394P213-port physical layer interface Data sheet status Data sheet Product Definition [1] status status Objective Development This data sheet contain...
Manual Details
| Brand | Philips |
|---|---|
| Pages | 28 |
| File Size | 155.56 KB |
| Published | July 12, 2026 |
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Frequently Asked Questions
What standard is this device compliant with regarding high-speed data transfer?
It fully supports the IEEE 1394–1995 Standard and Interoperable with FireWire implementations of IEEE Std 1394.
How does the PDI1394P21 manage power consumption in standby mode?
The device offers automatic device power down during suspend, and also includes features like Link interface disable via LPS to conserve energy.
Which voltages can this PHY be used with for other Physical Layers (PHYs)?
It is interoperable with other Physical Layers using both 3.3 V and 5 V supplies at speeds up to 400 Mbits/s.
What are the supported data rates for multispeed concatenation?
The device supports multispeed concatenation at 100/200/400 Mbits/s.