ML4824 User Guide - Fairchild Electronics

March 1998

Application Note 42045 ML4824, A Novel Method for

an Off-Line PFC-PWM Combo Controller

INTRODUCTION One of the most undesirable phenomena experienced by the other (SW1) turns off. They are “unsynchronized” utility companies is the high harmonic content of the line when both are switched on at the same time.) Here SW1 current. The harmonic content of this line current tends to and SW2 are switched on and off at the same time. The cause transformer overheating at the substations, which peak currents and therefore the ripple voltage are less are responsible for providing power to all sectors of a than a PFC stage with a resistive load. Even further given area. For three-phase distribution, neutral currents reductions are possible by “synchronizing” the 2 stages will flow in the presence of these harmonics. For single- (Figures 4 and 5). phase distribution, the narrow conduction angle demanded by capacitive input filters in switching power Micro Linear‘s ML4824 Combo Controller IC is an converters causes high harmonic content in the current integrated solution for systems benefitting from the waveform, resulting in lower operating efficiency. advantages made possible by synchronizing the 2

cascaded power stages. In this application note the

A viable solution to this problem is the inclusion of a differences between the traditional combo modulation power factor correction (PFC) stage to facilitate more scheme (unsynchronized or trailing edge modulation) and efficient power usage as well as lowering the harmonic the ML4824’s leading/trailing edge modulation scheme content of the line current. The most popular topology for are explained. A typical application is shown and test this task is the switched-mode boost converter. Here the results are compared with the traditional approach. Then, boost converter stage is inserted between the input a detailed look is taken inside the ML4824 and key rectifier and the bulk storage capacitor. This forces the design formulas are reviewed which will enable users to input current to be in phase with the input voltage and begin their own design. provides a boosted D.C. voltage reservoir for the following power stage. CASCADE POWER CONVERTER

In many instances the power supply system must interface The cascade connection of power stages is a very to a wide range input voltage (80-264V) requiring the effective and powerful tool in the design of state-of-the- boosted voltage be equal to or greater than 380VDC. art high frequency switch mode power converters (1). In For safe operation a capacitor with a voltage rating of at recent years, power factor corrected power converters are least 400V is necessary. Traditional cascaded power rapidly gaining popularity. They offer improved stages require large bulk capacitance values with low ESR performance when compared to traditional off-line to minimize peak to peak ripple voltage and lower self switching power converters. However, special system heating. Together these requirements result in a costly stability considerations must be made. capacitor.

Traditional trailing edge modulation results in a

To understand why the bulk capacitor requirements are momentary no-load condition when the buck switch is traditionally so stringent consider the circuit shown in turned off. This condition makes loop compensation Figure 1, a PFC power stage with resistive load. The bulk difficult as it results in 2 poles located close to the RHPZ capacitor C1 must supply load current I0 when VSW is (Right Half Plane Zero) already in play because the boost on, storing energy in the boost inductor L1. It must also inductor operates in continuous conduction current “absorb” the peak current from L1 each time VSW mode. Synchronous switching techniques as employed in switches off. The result of these currents into and out of the ML4824 push these poles further out in frequency C1 is a large ripple voltage across it. It is this large current allowing unity gain crossover to be placed at as high as with steep wavefronts that place the high demand on C1’s one-half the line frequency. bulk capacitance and ESR values to minimize output ripple. For example, consider a single power stage boost

converter as shown in Figure 1. The load of this stage is

Next, consider Figures 2 and 3, a PFC stage followed by connected to the output filter and its value affects the an “unsynchronized” PWM stage. (Note 1: In this note loop response of the converter. When the load is reduced, the terms “unsynchronized” and “synchronized” are used the poles due to the inductor and the capacitor become to describe the switching action of 2 power switches closer and the phase margin is reduced. operating from the same system clock. The switches are “synchronized” when one of them (SW2) turns on when

REV. 1.0 11/17/2000