TEXAS INSTRUMENTS SN65LVDS104, SN65LVDS105 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS Specifications

查询SN65LVDS104供应商 SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

Receiver and Drivers Meet or Exceed the

SN65LVDS104 SN65LVDS105 Requirements of ANSI EIA/TIA-644 D OR PW PACKAGE D OR PW PACKAGE (TOP VIEW) (TOP VIEW)

Standard – SN65LVDS105 Receives Low-Voltage TTL

EN1 1Y EN1 1Y

(LVTTL) Levels

EN2 1Z EN2 1Z

– SN65LVDS104 Receives Differential Input

EN3 2Y EN3 2Y

Levels, ±100 m V

VCC 2Z VCC 2Z

Designed for Signaling Rates up to

GND 3Y GND 3Y

630 Mbps

Operates From a Single 3.3-V Supply 4Y NC 4Y

Low-Voltage Differential Signaling With EN4 4Z EN4 4Z

Typical Output Voltage of 350 m V and a 100-Ω Load Propagation Delay Time logic diagram (positive logic) – SN65LVDS105 2.2 ns (Typ)

’LVDS104

– SN65LVDS104 3.1 ns (Typ)

Electrically Compatible With LVDS, PECL,

LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, EN1 EN2

SSTL, or HSTL Outputs With External 2Y Networks

Driver Outputs Are High Impedance When EN3

Disabled or With VCC <1.5 V

Bus-Pin ESD Protection Exceeds 16 k V

SOIC and TSSOP Packaging 4Y 4Z

description

’LVDS105

The SN65LVDS104 and SN65LVDS105 are a 1Y differential line receiver and a LVTTL input

(respectively) connected to four differential line

drivers that implement the electrical characteris- 2Y tics of low-voltage differential signaling (LVDS).

LVDS, as specified in EIA/TIA-644 is a data EN3

signaling technique that offers low-power, low- 3Y

noise coupling, and switching speeds to transmit 3Z data at speeds up to 655 Mbps at relatively long

distances. (Note: The ultimate rate and distance

of data transfer is dependent upon the attenuation 4Z

characteristics of the media, the noise coupling to the environment, and other system characteris- tics.) The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream. The SN65LVDS104 and SN65LVDS105 are characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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