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Cypress CY22393 CY22394 CY22395 Three-PLL Serial-Programmable Flash-Programmable Clock Generator User Manual, Specifications

Summary

This manual provides comprehensive technical documentation for a versatile Flash-Programmable Clock Generator family (CY22393, CY22394, CY22395). These advanced clock generators utilize three integrated PLLs to generate multiple unique and high-accuracy frequencies. Designed for demanding applications in multimedia, industrial controls, and communications, the devices offer sophisticated features like 0 ppm frequency generation, low jitter outputs, and field/in-system programmability. The guide covers detailed performance curves, configuration options, and system integration details crucial for engineers seeking highly precise clock solutions across various voltage levels.

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CY22393 CY22394 CY22395

Three-PLL Serial-Programmable Flash-Programmable Clock Generator

Features Benefits Three integrated phase-locked loops (PLLs) Generates up to three unique frequencies on up to six

outputs from an external source.

Ultra wide divide counters (8-bit Q, 11-bit P, and 7-bit post divide) Allows for 0 ppm frequency generation and frequency

conversion in the most demanding applications.

Improved linear crystal load capacitors

Improves frequency accuracy over temperature, age,

Flash programmability with external programmer

process, and initial ppm offset.

Field-programmable

Nonvolatile programming enables easy customization,

Low jitter, high accuracy outputs

ultra-fast turnaround, performance tweaking, design timing

Power management options (Shutdown, OE, Suspend) margin testing, inventory control, lower part count, and more

Configurable crystal drive strength secure product supply. In addition, any part in the family can be programmed multiple times, which reduces

Frequency select via three external LVTTL inputs

programming errors and provides an easy upgrade path for

3.3V operation existing designs. 16-pin TSSOP package In-house programming of samples and prototype quantities

Cy Clocks RT™ software support is available using the CY3672 FTG Development Kit. Production quantities are available through Cypress Advanced Features Semiconductor’s value-added distribution partners or by using third-party programmers from BP Microsystems, Hi Lo

I2C serial interface for in-system configurability Systems, and others. Configurable output buffer Performance suitable for high-end multimedia, communica-

Digital VCXO tions, industrial, A/D converters, and consumer applica- tions.

High frequency LVPECL output (CY22394 only)

Supports numerous low power application schemes and

3.3/2.5V outputs (CY22395 only)

reduces electromagnetic interference (EMI) by allowing unused outputs to be turned off. Adjust crystal drive strength for compatibility with virtually all crystals. 3-bit external frequency select options for PLL1, CLKA, and CLKB. Industry standard packaging saves on board space. Easy to use software support for design entry. I2C interface allows in-system programming into volatile configuration memory. All frequency settings can be changed, providing literally millions of frequency options. Adjust output buffer strength to lower EMI or improve timing margin. Fine tune crystal oscillator frequency by changing load capacitance. Differential output up to 400 MHz. Provides interfacing option for low voltage parts.

Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document #: 38-07186 Rev. *C Revised March 13, 2007

提供单片机解密、IC解密、芯片解密业务 010-62245566 13810019655

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Page Summary Contents For Cypress CY22393 CY22394 CY22395 Three-PLL Serial-Programmable Flash-Programmable Clock Generator User Manual, Specifications

Page 1 CY22393 CY22394 CY22395 Three-PLL Serial-Programmable Flash-Programmable Clock Generator Features Benefits Three integrated phase-locked loops (PLLs) Generates up to three unique frequencies on up to ...
Page 2 CY22393 CY22394 CY22395 Selector Guide Part Number Outputs Input Frequency Range Output Frequency Range Specifics CY22393FC 6 CMOS 8 MHz–30 MHz (external crystal) Up to 200 MHz Commercial Temperature ...
Page 3 CY22393 CY22394 CY22395 Logic Block Diagram — CY22395 XTALIN XTALOUT Divider LCLKE /2, /3, or /4 CONFIGURATION FLASH PLL1 11-Bit P 8-Bit Q Divider LCLKD SHUTDOWN/OE 7-Bit Crosspoint Divider S2/SUSPEND...
Page 4 CY22393 CY22394 CY22395 Pin Definitions (continued) Pin Number Pin Number Pin Number Name Description CY22393 CY22394 CY22395 CLKB or LCLKB Configurable clock output B; LCLKB referenced to LVDD CLKA o...
Page 5 CY22393 CY22394 CY22395 Digital VCXO associated logic, while suspending an output simply forces a tri-state condition. The serial programming interface is used to dynamically change the capacitor load...
Page 6 CY22393 CY22394 CY22395 program an inactive register, and then transition to that Xbuf_OE register. This allows these resources to stay active during This bit enables the XBUF output when HIGH. For th...
Page 7 CY22393 CY22394 CY22395 PLL*_En applied, or after shutdown is released. If in doubt, use the next higher setting. This bit enables the PLL when HIGH. If PLL2 or PLL3 are not enabled, then any output s...
Page 8 CY22393 CY22394 CY22395 Addr S2 (1,0) b7 b6 b5 b4 b3 b2 b1 b0 40H PLL1_Q[7:0] 41H PLL1_P[7:0] 42H Div Sel PLL1_En PLL1_LF[2:0] PLL1_PO PLL1_P[9:8] 43H PLL1_Q[7:0] 44H PLL1_P[7:0] 45H Div Sel PLL1_En P...
Page 9 CY22393 CY22394 CY22395 Start Sequence - Start Frame is indicated by SDAT going LOW (HIGH). There are three basic read operations: current when SCLK is HIGH. Every time a start signal is given, the ne...
Page 10 CY22393 CY22394 CY22395 Figure 2. Data Frame Architecture 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit 1 Bit Slave Slave Slave Slave Slave Slave Slave Slave SDAT Write R/W = 0 ACK ACK ACK ACK ACK A...
Page 11 CY22393 CY22394 CY22395 Serial Programming Interface Timing Figure 4. Start and Stop Frame Transition START to next Bit STOP Figure 5. Frame Format (Device Address, R/W, Register Address, Register Dat...
Page 12 CY22393 CY22394 CY22395 Operating Conditions[2] Parameter Description Part Numbers Min Typ Max Unit VDD/AVDD/LVDD Supply Voltage All 3.135 3.3 3.465 LVDD 2.5V Output Supply Voltage CY22395 2.375 2.5 2...
Page 13 CY22393 CY22394 CY22395 3.3V Switching Characteristics Parameter Description Conditions Min Typ Max Unit 1/t1 Output Frequency[4, 6] Clock output limit, CMOS, Commercial MHz Clock output limit, CMOS, ...
Page 14 CY22393 CY22394 CY22395 Switching Waveforms Figure 6. All Outputs, Duty Cycle and Rise/Fall Time OUTPUT Figure 7. Output Tri-state Timing ALL TRI-STATE OUTPUTS Figure 8. CLK Output Jitter CLK OUTPUT F...
Page 15 CY22393 CY22394 CY22395 Test Circuit Figure 11. Test Circuit AV DD CLK out CLOAD P+/P- out (L)V DD Ordering Information Ordering Code Package Type Product Flow CY22393ZC-XXX 16-pin TSSOP Commercial, 0...
Page 16 CY22393 CY22394 CY22395 Ordering Information (continued) Ordering Code Package Type Product Flow CY22393FXI 16-pin TSSOP Industrial, –40 to 85°C CY22393FXIT 16-pin TSSOP - Tape and Reel Industrial, –4...
Page 17 CY22393 CY22394 CY22395 Document History Page Document Title: CY22393/CY22394/CY22395 Three-PLL Serial-Programmable Flash-Programmable Clock Generator Document Number: 38-07186 Orig. of REV. ECN NO. I...

Manual Details

Brand Cypress
Pages 17
File Size 317.39 KB
Published May 18, 2026
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Frequently Asked Questions

How can the device be programmed and customized?

It is flash programmable using an external programmer or configured in-system via the IC serial interface.

Does it support low voltage or high frequency output standards?

Yes, it supports 2.5V/3.3V outputs (CY22395) and provides a high frequency LVPECL output (CY22394).

How can I improve signal quality or stability for my design?

You can fine-tune crystal frequency by changing load capacitance, or reduce EMI by adjusting the unused outputs.

Is this device suitable for life-support systems or critical control applications?

No. It is not warranted and generally unsuited for medical, life support, or critical safety applications without written agreement.