ATMEL AT45DB011B User Guide
Summary
This low-power Serial Peripheral Interface (SPI) Flash memory is engineered for reliable data and code storage in demanding commercial and industrial embedded systems. Featuring 1MB of non-volatile memory and an integrated SRAM buffer, it supports efficient programmability without requiring high voltages. The accompanying manual provides comprehensive details on the device's architecture, including sector, block, and page programming methods. It guides developers through utilizing the simple three-wire interface (CS/SCK/SI) for optimal integration, ensuring robust system reliability in low-voltage applications.
Page 1 Text Content
Features Single 2.7V - 3.6V Supply Serial Peripheral Interface (SPI) Compatible 20 MHz Max Clock Frequency Page Program Operation Single Cycle Reprogram (Erase and Program) 512 Pages (264 Bytes/Page) Main Memory Supports Page and Block Erase Operations One 264-byte SRAM Data Buffer Continuous Read Capability through Entire Array Ideal for Code Shadowing Applications 1-megabit Fast Page Program Time – 7 ms Typical 120 µs Typical Page to Buffer Transfer Time
2.7-volt Only
Low Power Dissipation 4 m A Active Read Current Typical
Data Flash®
2 µA CMOS Standby Current Typical Hardware Data Protection Feature 100% Compatible with AT45DB011 Commercial and Industrial Temperature Ranges
AT45DB011B
Green (Pb/Halide-free/Ro HS Compliant) Packaging Options
Description The AT45DB011B is a 2.7-volt only, serial interface Flash memory ideally suited for wide variety of digital voice-, image-, program code- and data-storage applications. Its 1,081,344 bits of memory are organized as 512 pages of 264 bytes each. In addi- tion to the main memory, the AT45DB011B also contains one SRAM data buffer of 264 bytes. The buffer allows receiving of data while a page in the main memory is being reprogrammed. EEPROM emulation (bit or byte alterability) is easily handled with a self-contained three step Read-Modify-Write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel inter- face, the Data Flash uses a SPI serial interface to sequentially access its data. SPI mode 0 and mode 3 are supported. The simple serial interface facilitates hardware
Pin Configurations CBGA Top View through Package
Pin Name Function
AT45DB011B
CS Chip Select
SCK Serial Clock SCK GND VCC Preliminary 16-
SI Serial Input CS RDY/BSY WP
Megabit 2.7-volt
SO Serial Output SO SI RESET
Only Serial
WP Hardware Page
Write Protect Pin
Data Flash
RESET Chip Reset TSSOP Top View Type 1
RDY/BUSY Ready/Busy
RDY/BUSY CS SOIC RESET NC WP NC VCC NC
SI SO
GND NC
SCK GND
SCK NC
RESET VCC
SO SI
CS WP
Rev. 1984I–DFLSH–9/7/05
Page Summary Contents For ATMEL AT45DB011B User Guide
Manual Details
| Brand | Atmel |
|---|---|
| Pages | 32 |
| File Size | 449.42 KB |
| Published | May 15, 2026 |
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Frequently Asked Questions
What external components are required to access the data?
The device uses a three-wire serial interface consisting of Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK), controlled by the Chip Select pin (CS).
Does this chip require separate erase cycles before programming data?
No, all programming cycles are self-timed, and no separate erase cycle is required before programming.
What is the low current draw capability for standby mode?
The typical CMOS Standby Current is very low at 2 µA.